Vlang is an opensource multicore-enabled verification language built on top of the D Programming Language
  • Complete port of Universal Verification Methodology (UVM)
  • Can coexist with SystemVerilog UVM testbenches
  • ABI Compatibility with C/C++
  • Multi-Core Enabled parallel simulations
  • Seemless integration with SystemVerilog, VHDL and SystemC
  • BDD based constraint solver
  • Multiple Parallel Simulators and Multiple UVM Roots
  • Clean syntax without macros and preprocessing
  • Super fast compilation
  • Presently the only multicore parallel UVM implementation
  • Generic and Generative programming paradigms


Example Code Snippet

class apb_rw: uvm_sequence_item
  mixin uvm_object_utils;
  enum kind_e {READ, WRITE};
  @rand uint addr;
  @rand uint wdata;
  @rand kind_e kind;
  uint rdata;
  this(string name = "apb_rw") {
  Constraint! q{
    addr < 4;
  } addr_range;

Vlang Articles

Vlang, yet another Verification Language! Nov 5 2015

Ten years ago, IEEE ratified a new standard for Hardware Verification Language named SystemVerilog. Since then, SystemVerilog has come a long way. Millions of lines of code have been written in SystemVerilog...